1. Field of the Invention
The present invention relates to an image processing device for binary or multi-level digital encoding of an image signal for use in a digital copier, an electronic file or the like.
2. Description of the Prior Art
The conventional device of this sort is composed of a comparator circuit for comparing an image signal with a reference signal, in which density adjustment of the output signal is achieved by rendering said reference signal variable, while a pseudotonal rendition is obtained by varying said reference signal according to a certain rule in synchronization with the image signal.
An example of such conventional image signal processing circuit is shown in FIG. 1.
Each of blocks 1, 2 respectively surrounded by broken lines performs binary encoding, and a multi-level encoding such as ternary or quaternary encoding is attained by increasing the number of said blocks. A comparator circuit 10 or 20 compares an input image signal with a multi-level reference signal supplied from a selector 11 or 21 and releases the result of said comparison.
The selector 11 or 21 selects either a fixed reference signal or a reference signal for pseudotonal reproduction. A latch circuit 13 or 23 generates a fixed reference signal as a slice level for binary encoding and is composed for example of a central processing unit or a dip switch.
A dither read-only memory (ROM) 12 or 22 stores reference signals, preferably plural sets thereof, for pseudotonal reproduction, and memorizes plural dither patterns in advance. A main scanning counter 30 controls the synchronization in the main scanning direction by counting pixel clock signals entered in synchronization with the image signal to be compared with a selected dither pattern. A latch circuit 32 selects one of the plural dither patterns stored in the dither ROM 12 or 22 according, for example, to the image quality.
In the circuit shown in FIG. 1, a multi-level digital encoding requires the blocks 1, 2 of a number corresponding to the number of levels, for example two blocks for ternary encoding or three blocks for quaternary encoding. Consequently, the magnitude of the circuit increases for a large number of levels.
Also, in the case of a multi-level signal conversion to obtain signals such as 00, 01, 10, 11 in binary numbers, an encoding of the binary encoded image signals obtained from said blocks has to be made through a very large circuit which is, practically, unacceptable.
Furthermore, such comparator circuit is inadequate for high-speed processing of an image signal with a large amount of data such as 14 or 16 bits since the delay time in processing is increased due to the serial connection of the circuits. The use of high-speed logic elements should allow one to avoid this drawback, but gives rise to a very high cost.